When cache is disabled, then typically exclusive ops are passed as is direct to the interconnect the core is plugged into. In this case it appears that the SOC doesn't implement an exclusive monitor, but did at least remember to generate aborts for these operations
When cache is disabled, then typically exclusive ops are passed as is direct to the interconnect the core is plugged into. In this case it appears that the SOC doesn't implement an exclusive monitor, but did at least remember to generate aborts for these operations
Very smart debugging step to switch to standard load and store. This is often missed. A bit of forest for the trees.