I'm starting to believe in Qualcomm! The Snapdragon X2 Elite Extreme is alas only available in a single system, with it's tri-channel on-package (!) memory good for 228 GB/s. But it's a beast. The core is just good, even in the mainstream form in other systems: some of the best single core performance you can get, shy of Apple.
And they are upstreaming their stuff much better! They hired a bunch of really good known FOSS developers and it seems to be working!
Now they are talking up High Bandwidth Compute as their next big thing. And I want to believe, even if it makes me nervous that they too intend to leave consumer computing completely in the dust. https://www.qualcomm.com/news/onq/2026/11/qualcomm-hbc-valid...
This is, as commented, at M4 Max levels of GB/s. It is not impressive. It has some uses! But if this was their modern opening salvo I would not be impressed.
> tri-channel on-package (!) memory good for 228 GB/s
Why is on-package memory impressive/better in this case? It's one channel more than your typical consumer x86 system (192-bit bus vs 128-bit) which is something but you could technically have quad channel with two LPCAMM2 sockets?
Yeah, this thing is unusual. It resembles a consumer GPU but using normal DRAM with more channels, so then you get more RAM but less memory bandwidth than GDDR/HBM, which is the same thing Apple does. And the TDP is pretty attractive for what it is.
But what is that amount of SRAM for? It simultaneously seems like a lot, because SRAM is so expensive, but still not very much, because what can you fit in 0.5GB? Is there a specific workload that needs something that looks like this?
0.5 GB of SRAM is exactly what the Cuckatoo32 [1] Proof-of-Work scheme needs for optimal solving efficiency. Solutions are 42-cycles in random bipartite graphs of 2^32 edges on 2^32 + 2^32 nodes, which can be found by repeatedly removing edges that have only one adjacent edge. Tracking which nodes have incident edges takes 2^32 (completely randomly accessed) bits which is exactly 0.5GB. Another 0.5 GB is needed to track alive edges but those can be accessed serially for which DRAM suffices.
The Intel D270, Nvidia DGX Spark, and (somewhat) AMD Strix Halo also use the same approach, so it seems to be getting pretty common.
SRAM wise it doesn't seem too insane. About the same ratio of memory:SRAM as the 5090 (IIRC). Still more than I would have expected. I assume they found it helps process the current layer faster or something.
Ok so it’s significantly worse than Apple M6 and we don’t know if it’s cheaper or not
Edit: Ah sorry you’re right, the bandwidth is lower but the TOPS is a lot higher. I’m not sure how much effect you get from higher TOPS with such low bandwidth though.
> I’m not sure how much effect you get from higher TOPS with such low bandwidth though.
Raised arithmetic intensity. It would be quite good for LLM prefill, and decode would want to adapt by pushing parallelism higher (saving on memory bandwidth by reusing the same layer weights for multiple streams) or, if unable to do so (e.g. due to KV cache constraints) by resorting to speculative decoding (where the expensive 'validate' step handles tokens in parallel within a single stream). It does not make the platform inherently unviable. It would also do well at other tasks such as image/video generation, which is already quite compute bound.
Aren't these specs already outdated? Seems meh. I would think players would like to bring something new to the table instead of bringing what was okay two years ago or so.
Give me 1TB RAM and 5TB/s or something that exciting.
For most purposes, this seems reasonable? This looks like a single-height card, so fitting four of these in a workstation or server would give 512 GB RAM and 2 TB/s total bandwidth. That's pretty attractive for a lot of current LLMs, even if one wishes for 1 TB capacity at 5 TB/s bandwidth.
But this gives you significantly more memory capacity for a compute/vram bandwidth tradeoff (i.e. arithmetic intensity) that's ultimately comparable to Blackwell, perhaps even more skewed towards compute. This seems good if you care about being able to store larger sparse models and more KV caches because that ultimately bottlenecks your ability to do inference.
Maybe. I don't know power for the MI350, but the RTX PRO 6000 is normally a 200-300W card, so you pay 2x the power for 3/4th the RAM and 3x the bandwidth. The performance frontier looks very different in terms of power to hold a mid-size model and throughout per user or across users. Price and inference stack would be big factors in what I would choose.
MI350P, H200 NVL and Nvidia RTX PRO 6000 are all 600W but compute wise all of them should be 3 to 4 times more performant than A100 Ultra according to their specifications.
600w is way off the vf curve though... Tiny bit of tuning and you'll get ~80-90% of the performance at ~150w nominal. At least that's what I got out of some pro 6000s when I spent 15 mins to underclock it.
> I would think players would like to bring something new to the table instead of bringing what was okay two years ago or so.
Speaking of... from [0]:
Introducing Qualcomm Cloud AI 100 Ultra
High performance and cost-optimized cloud AI inferencing for generative AI
Written by
Rashid Attar
Nov 13, 2023
Today we announce the Qualcomm Cloud AI 100 Ultra, a new member of our portfolio of cloud artificial intelligence (AI) Inference cards, purpose-built for generative AI and large language models (LLMs). ...
What exactly do you propose they do? Do you think they are holding back supply? Should they sell at less than market price? That's just handing the profits to scalpers/middle men.
I'm sure NVIDIA, AMD, Intel, Qualcomm, etc. would sell more hardware if they could, but they can't.
It may be a semantic thing but I don't think bandwidth pooling works like that? Unless your blocks are distributed perfectly between cards there's going to be data passed between each card and from VRAM to compute. Correct me if I'm wrong though
I think the way it works is that the weights have to get streamed through the compute and the weights can be split very easily. With multiple cards you do have a coordination/communication phase after each layer of weights but that's usually much less significant than the compute phase.
It depends on how you slice the weights. You can split along layers which means each GPU waits for the previous one to finish or you can split the tensors across gpus.
Splitting the tensors is closer to n times the effective vram bandwidth but there are still overhead, sync waits, and reduce steps that eat away at the overall performance.
If the specs seem outdated, it’s because this chip launched in 2024. It’s available at cloud providers including Cirrascale
Given the rush to dig MI50s and V100s out of the trash and press them into service, 2024 seems like future space alien technology.
Holy cow the v100s go for like $1k on ebay now... They were selling for $100 or less a couple years ago.
Thats relieving!
I'm starting to believe in Qualcomm! The Snapdragon X2 Elite Extreme is alas only available in a single system, with it's tri-channel on-package (!) memory good for 228 GB/s. But it's a beast. The core is just good, even in the mainstream form in other systems: some of the best single core performance you can get, shy of Apple.
And they are upstreaming their stuff much better! They hired a bunch of really good known FOSS developers and it seems to be working!
Now they are talking up High Bandwidth Compute as their next big thing. And I want to believe, even if it makes me nervous that they too intend to leave consumer computing completely in the dust. https://www.qualcomm.com/news/onq/2026/11/qualcomm-hbc-valid...
This is, as commented, at M4 Max levels of GB/s. It is not impressive. It has some uses! But if this was their modern opening salvo I would not be impressed.
> I'm starting to believe in Qualcomm
Someone drop the YouTube link of their robot presentation
The way it drops is priceless.
https://youtube.com/shorts/aZmt5E151Bk
Those guys were fast on the draw to cover the body with those sheets.
He’s hired to follow the robot and put the sheet on it whenever it’s dropped down to the floor
> tri-channel on-package (!) memory good for 228 GB/s
Why is on-package memory impressive/better in this case? It's one channel more than your typical consumer x86 system (192-bit bus vs 128-bit) which is something but you could technically have quad channel with two LPCAMM2 sockets?
Buy for the low, low price of - nope. Not for you.
ref: https://cloud-gpus.com/qualcomm-ai-100-ultra/At $5 per hour these are absolutely terrible value. You can rent an H200 for that price and an H200 is much better in every way. Weird
Not if the customers cannot rent a H200 (because they have been told not to rely on foreign gpus)
I guess they get their customers on scale, can you get hundreds of h200?
What's the price?
According to their own website, they cost 1 cent.
Less than I expected for this level of GPU power.
It's a trend I like.
8,750 in stock at 1 cent, too. The more expensive 47 and 63 cent variants are all sold out.
Yeah, I clicked that too. But knowing qualcomm they obviously cost an arm and a leg. Still interesting how much.
My research indicates the price is $10-17K USD.
that tracks, $0.01 for chip, and $9999.9 for the memory
I mean at ten bucks it’s not a bad deal but that’s quite a range.
Honestly, let me buy one, it's many times faster than the minipc I run local ai on so if the price is right I'm in.
hopefully less than 5090?
Not a chance.
Curious how the memory bandwidth actually holds up under sustained inference loads compared to the spec sheet numbers.
that's a slim card
Sort of interesting design It has half a terabyte of SRAM on the accelerator with a 128 GB of RAM replacing HBM with SRAM but keeping regular RAM.
half a gigabyte not terabyte lol
Yeah, this thing is unusual. It resembles a consumer GPU but using normal DRAM with more channels, so then you get more RAM but less memory bandwidth than GDDR/HBM, which is the same thing Apple does. And the TDP is pretty attractive for what it is.
But what is that amount of SRAM for? It simultaneously seems like a lot, because SRAM is so expensive, but still not very much, because what can you fit in 0.5GB? Is there a specific workload that needs something that looks like this?
0.5 GB of SRAM is exactly what the Cuckatoo32 [1] Proof-of-Work scheme needs for optimal solving efficiency. Solutions are 42-cycles in random bipartite graphs of 2^32 edges on 2^32 + 2^32 nodes, which can be found by repeatedly removing edges that have only one adjacent edge. Tracking which nodes have incident edges takes 2^32 (completely randomly accessed) bits which is exactly 0.5GB. Another 0.5 GB is needed to track alive edges but those can be accessed serially for which DRAM suffices.
[1] https://github.com/tromp/cuckoo
The Intel D270, Nvidia DGX Spark, and (somewhat) AMD Strix Halo also use the same approach, so it seems to be getting pretty common.
SRAM wise it doesn't seem too insane. About the same ratio of memory:SRAM as the 5090 (IIRC). Still more than I would have expected. I assume they found it helps process the current layer faster or something.
So it's an M4 Max Mac Studio, RAM-wise, with a GPU's worth of compute?
(I know it's you comparing it to the M4 Max, not them, but:) it's Qualcomm, so it'll be compared to the M4 Max, while being slower than a M2 Max.
Seems like a reasonable general-purpose card.
Ok so it’s significantly worse than Apple M6 and we don’t know if it’s cheaper or not
Edit: Ah sorry you’re right, the bandwidth is lower but the TOPS is a lot higher. I’m not sure how much effect you get from higher TOPS with such low bandwidth though.
> I’m not sure how much effect you get from higher TOPS with such low bandwidth though.
Raised arithmetic intensity. It would be quite good for LLM prefill, and decode would want to adapt by pushing parallelism higher (saving on memory bandwidth by reusing the same layer weights for multiple streams) or, if unable to do so (e.g. due to KV cache constraints) by resorting to speculative decoding (where the expensive 'validate' step handles tokens in parallel within a single stream). It does not make the platform inherently unviable. It would also do well at other tasks such as image/video generation, which is already quite compute bound.
Apple M6 has 80-100 TOPS.
Qualcomm Cloud AI 100 Ultra has 800 TOPS, almost 10 times more.
This could be very fast at running embedding models (if it supports the right modes)
Considering that memory bandwidth is the most important for inference for most neural networks, that matters more.
Modern inference stacks use different GPUs for decode versus prefill. This is a GPU suitable for prefill.
is this hexagon?
Yeah, bunch of HTPs
Aren't these specs already outdated? Seems meh. I would think players would like to bring something new to the table instead of bringing what was okay two years ago or so.
Give me 1TB RAM and 5TB/s or something that exciting.
For most purposes, this seems reasonable? This looks like a single-height card, so fitting four of these in a workstation or server would give 512 GB RAM and 2 TB/s total bandwidth. That's pretty attractive for a lot of current LLMs, even if one wishes for 1 TB capacity at 5 TB/s bandwidth.
If you are going down this path, MI350P and RTX PRO 6000 Blackwell is what you would want. A lot more compute a lot more vram bandwidth.
> A lot more compute a lot more vram bandwidth.
But this gives you significantly more memory capacity for a compute/vram bandwidth tradeoff (i.e. arithmetic intensity) that's ultimately comparable to Blackwell, perhaps even more skewed towards compute. This seems good if you care about being able to store larger sparse models and more KV caches because that ultimately bottlenecks your ability to do inference.
Maybe. I don't know power for the MI350, but the RTX PRO 6000 is normally a 200-300W card, so you pay 2x the power for 3/4th the RAM and 3x the bandwidth. The performance frontier looks very different in terms of power to hold a mid-size model and throughout per user or across users. Price and inference stack would be big factors in what I would choose.
MI350P, H200 NVL and Nvidia RTX PRO 6000 are all 600W but compute wise all of them should be 3 to 4 times more performant than A100 Ultra according to their specifications.
https://www.servethehome.com/the-amd-instinct-mi350p-is-a-hb...
600w is way off the vf curve though... Tiny bit of tuning and you'll get ~80-90% of the performance at ~150w nominal. At least that's what I got out of some pro 6000s when I spent 15 mins to underclock it.
But there are already plenty of products for most purposes.
> I would think players would like to bring something new to the table instead of bringing what was okay two years ago or so.
Speaking of... from [0]:
[0] <https://www.qualcomm.com/news/onq/2023/11/introducing-qualco...>5 year old GPUs are still at crazy prices.
Plenty of businesses want in local inference and are priced out.
You can't do quality inference on such a toy. It's a myth.
A great opportunity for huawei
Nobody helps China like American corps helps China. Domestic anticompetitive behavior spurs demand for international competition
What exactly do you propose they do? Do you think they are holding back supply? Should they sell at less than market price? That's just handing the profits to scalpers/middle men.
I'm sure NVIDIA, AMD, Intel, Qualcomm, etc. would sell more hardware if they could, but they can't.
This is all the CPU companies playing catch up with Nvidia and AMD.
The thing you are describing is much closer to AMD and Nvidia latest generation server offerings.
See MI455X for the absolute cutting edge and MI350P for something you can use outside of a datacenter.
8 of those cards give you 1TB of ram and 4.4TB/s
It may be a semantic thing but I don't think bandwidth pooling works like that? Unless your blocks are distributed perfectly between cards there's going to be data passed between each card and from VRAM to compute. Correct me if I'm wrong though
I think the way it works is that the weights have to get streamed through the compute and the weights can be split very easily. With multiple cards you do have a coordination/communication phase after each layer of weights but that's usually much less significant than the compute phase.
It depends on how you slice the weights. You can split along layers which means each GPU waits for the previous one to finish or you can split the tensors across gpus.
Splitting the tensors is closer to n times the effective vram bandwidth but there are still overhead, sync waits, and reduce steps that eat away at the overall performance.